1. Field of the Invention
The present invention relates to a memory module and components thereof, and a wire layout method.
2. Description of the Related Art
In recent years, higher speeds have been difficult to achieve for large-capacity memory module products. A large capacity DRAM implies a problem in which it cannot be operated at high speeds due to an excessively large load capacity of the DRAM which is driven at one time, with respect to the length of wires from a memory controller to the DRAM, causing limitations to the trend of higher speeds sought for large-capacity products of memory systems, so that new technologies are required for seeking larger capacities and higher speeds for memory modules.
JEDEC (Joint Electron Device Engineering Council) Semiconductor Technology Association (hereinafter called “JEDEC”) has discussed a technology referred to as LR-DIM (Load Reduce Dual Inline Memory Module) for seeking larger capacities and higher speeds. LR-DIMM is in a connector pin assignment of a connector for RDIMM (Registered Dual Inline Memory Module) which is mounted with a conventional DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).
RDIMM mounted with DDR3-SDRAM is generally referred to as DDR3-RDIMM, DDR3-Reg.DIMM or the like. In the following, DDR3-SDRAM is herein abbreviated simply as DRAM.
LR-DIMM includes RDIMM with a standard outer shape having a height of 18.75 mm, referred to as “VLP (Very Low Profile)-RDIMM,” other than one with a JEDEC standard outer shape having a height of 30 mm, referred to as “LP (Low Profile)-RDIMM.”
From the fact that VLP-RDIMM, due to its low-profile board, provides less space available for mounting parts as well as less space available for wiring on the board, as compared with LP-RDIMM, a high-level, high-density wiring technology, different from LP-RDIMM, is required for the new LR-DIMM technology.
For facilitating a description of LR-DIMM, DDR3-RDIMM will be briefly described with reference to FIG. 1 which shows the structure of RDIMM. DDR3-RDIMM will hereinafter be abbreviated as “RDIMM.”
FIGS. 1(a), 1(b) are a plan view showing a first surface and a second surface, opposite to the first surface, of RDIMM, respectively. RDIMM comprises board 1 which is PCB (Printed Circuit Board), and DRAMs 10-27, register (buffering device) 28, connectors 2-6, and termination resistors 7, 8, which are provided on board 1.
Register 28 has a function of redriving a command, an address, a control signal, and a clock signal. While the example shown in FIG. 1 comprises one register 28, two such registers may be provided. Termination resistors 7, 8 provided at both ends of board 1 serve as terminations for signals redriven to register 28.
In FIG. 1, the numbers of DRAMs (10-27) and registers (28) are dominated by a laminated structure of the DRAMs and I/O configuration. The example shown in FIG. 1 is 1-Rank RDIMM with DIMM in an I/Ox72 configuration, which is mounted with 18 DRAMs each in an I/Ox4 configuration and one register 28.
1-Rank means that an associated RDIMM is controlled by a single chip select signal (CS signal) from a memory system. When RDIMM is controlled by two CS signals, it is classified into 2-Rank. When controlled by four CS signals, RDIMM is classified into 4-Rank.
Since the structure of the connectors has an important meaning in the present invention, a brief description will be given of the structure of the connectors. The connectors of RDIMM have 240 pins in total. A pin at the left-hand end, when a board is viewed from a first surface, is designated “pin 1,” a pin at the right-hand end is designated “pin 120,” and a pin at the back of the 1-pin on the second surface is designated “pin 240.”
The connectors can be generally divided into connectors 2-5 which serve as a data section (DQ section); connector 6 which serves as a command, address, control signal and clock section (CA section); and another section including VSS, VDD, VTT, VREF, DQ, VREFCA, not shown.
FIGS. 2 and 3 are top plan views showing a wiring structure of RDIMM.
When board 1 is viewed from the first surface, there are 32 pins DQ[31:0], 8 pins CB[7:0], and data strobe signals (DQS) DQS[3:0], DQS[12:9], True/Bar of DQS 8 and DQS 17, for a total of 20 pins (not shown), in top and bottom connectors 2, 3 on the left side of connector 6 (CA section), so that there are a total of 60 signals.
When board 1 is viewed from the first surface, there are 32 pins DQ[63:32], and a True/Bar pins of DQS [7:4] and DQS[16:13], for a total of 16 (not shown), in connector terminals 4, 5 on the right side of connector 6 (CA section) on the top and bottom of board 1, i.e., there are a total of 48 signals. There are a total of 108 DQ and DQS signals on the left and right sides. CA signals include a total of 29, A[15:0], BA[2:0], #RAS, #CAS, #WE, CKE[1:0], ODT[1:0], #CS[n:0] (n=3 or 7), CLK, #CLK, Parity_in, #RESET, plus 4 or 8 signals. A series of DQ signals begins with the left end of the board on the top side, designated as DQ0, and runs toward the right end up to DQ63. CB[7:0] is positioned near the left side of connector 6 near the center of the board.
In conformity to the structure of the connectors, RDIMM has register 28 positioned above (near) connector 6 (CA), and DRAMs 10-27 positioned on both sides thereof. The DRAMs are not equal in number on the left and right sides of register 28, and particularly on the left side, DRAMs 14 and 23 are positioned in a central area of the board for receiving CB[7:0] for ECC (Error Check Correct). Also, DQ signals received by the DRAMs are assigned smaller numbers from the left-most DQ in accordance with the positional shifting of DQ terminals in connectors 2-5.
The wiring structure of RDIMM will be described with reference to FIGS. 2 and 3. First, the wiring structure for CA signals will be described with reference to FIG. 2. CA signal 29 input to register 28 is once redriven into register 28 and output therefrom. Output signals 30, 31 are transmitted, while daisy chaining the DRAMs (commonly referred to as “fly-by”), through the respective DRAMs tied in a row, and are terminated at a terminal potential (VTT, not shown) through termination resistors 7, 8.
FIG. 2 shows some of the numerous DRAM connection methods.
Next, the wiring structure of DQ signals will be described with reference to FIG. 3. In FIG. 3, bi-directional DQ signals 33-41 are transmitted between connectors 2, 3, connectors 4, 5, and respective DRAMs 10-27. For DQ signals 33-41, DQ represents a bi-directional high-speed I/O interface. Here, DQ signal 33 represents a connecting situation of eight DQs, two DQSs, and two /DQSs (“/” represents an inverted input).
The RDIMM of this example is a 1-Rank RDIMM having an I/Ox4 configuration, where DQ[3:0], DQS0, and /DQS0 are connected to DRAM 10, and DQ[7:4], DQS9, and /DQS9 are connected to DRAM 19. As to DQ signals 34-41, four DQs, one DQS, and one /DQS are connected, respectively, to each DRAM in a similar manner.
Connectors 2 and 3 are connected to the DRAMs, by 40 DQs, 10 DQSs, and 10 /DQSs, represented by DQ group 32. Connectors 4 and 5 are connected to the DRAMs, by 32 DQs, 8 DQSs, and 8 /DQSs, represented by DQ group 33. The wiring structure of the RDIMM is generally as described above.
Next, LR-DIMM of VLP type will be described with reference to FIG. 4. FIGS. 4(a), 4(b) show plan views of LR-DIMM of VLP type, when viewed from a first surface and a second surface, opposite to the first surface, respectively.
In the first place, LR-DIMM is mounted with an LR buffer which has a function of redriving DQ as well together with the CA section, and is intended to drive a large-capacity DIMM at high speeds by redriving DQ signals from a system. The LR-DIMM shown in FIG. 4 is a 2-Rank DIMM which is mounted with laminated DRAMs having an I/Ox4 configuration.
In LR-DIMM shown in FIG. 4, connectors have the same shape as those of RDIMM. LR-DIMM comprises LR buffers 69, 70 for redriving DQ and CA signals. In LR-DIMM, the LR buffers cannot receive 108 DQ and DQS signals at one time due to the limitations of their PKG structure.
Each of LR buffers 69, 70 is configured to be capable of receiving 40 DQ signals and 20 DQS signals. Each LR buffer is capable of receiving all CA signals. LR buffer 69, 70 outputs signals redriven thereby in a one-to-one relationship with respect to the inputs. In FIG. 4, the LR buffers are mounted in a left region on the top of board 1 and in a right region on the bottom of board 1, respectively, and 18 DRAMS 51-68 are mounted on both sides of the LR buffers.
Wiring structures within the board of FIG. 4 will be described with reference to FIGS. 5 and 6. First, a wiring structure for CA signals will be described with reference to FIG. 5. First, CA signal 71 from connector 6 is once distributed to LR buffer 70, and then applied to LR buffer 69. This results in a timing shift in the CA signals which reach LR buffers 69, 70.
CA signal 71 applied to LR buffer 69, 70 is transmitted through the respective DRAMs tied in a row, in a manner similar to RDIMM, and is terminated to a termination potential (VTT, not shown) at termination register 7 or 8. FIG. 5 shows how CA signals 72, 73 output from LR buffers 69, 70 are transmitted through the DRAMs.
CA signal 73 which has passed through LR buffer 69 once travels to the end of board 1, turns back from there, passes through DRAMs 51 and 60→51 and 61→62→53 and 63→54 and 64→55, and is terminated at termination register 8. Likewise, CA signal 72 which has passed through LR buffer 70 once travels to the end of board 1, turns back from there, passes through DRAMs 59 and 68→58 and 67→57→56 and 66→65, and is terminated at termination resistor 7. As can be seen from the way DRAMs 51-68 are connected, CA signals 72, 73 are not uniform in load due to the difference between distances traveled thereby.
Next, a wiring structure for DQ signals is shown with reference to FIG. 6. Interfaces 74, 75 for transmitting DQ and DQS signals from connectors 2-5 are bi-directional high-speed I/O interfaces, similar to those of RDIMM. However, unlike RDIMM, DQ and DQS signals 74, 75 from the connectors are not directly connected to DRAMs, but are passed once through LR buffers 69, 70 which divide DQ and DQS signals 74, 75 into a set of four DQs, one DQS, and one /DQS, which is directed to each DRAM.
Among the DQ signals, DQ[31:0], CB[7:0] and DQS[3:0], DQS[12:9], DQS 8 and DQS 17 are applied to LR buffer 69, while DQ[32:63] and DQS[7:4], DQS[16:13] are applied to LR buffer 70. Connectors 2 and 3 are connected to LR buffer 69, by 40 DQs, 10 DQSs, and 10 /DQS, represented by DQ group 74. Connectors 4 and 5 are connected to LR buffer 70, by 32 DQs, 8 DQSs, and 8 /DQSs, represented by DQ group 75.
The LR-DIMM described above has the following problems.
1. The LR buffer requires long wiring paths for outputting CA signals. It is known that when the output of the LR buffer is followed by long aggregate wiring paths, a large ring-back generally occurs in a DRAM at a distal end, and this can be said to constitute a factor for degrading the reliability of transmission quality.
2. Allocated loads (DRAMs) are not uniformly distributed to CA signal outputs of the LR buffer. Discontinuity of loads causes discontinuity of execution characteristic impedance (which includes taking into consideration on the influence of a capacitive load placed on a wire added to characteristic impedance Zo originally exhibited by the wire. It is generally known that the capacitive load causes an impedance exhibited by a wire itself to be lower than its original value), which can constitute a factor for degrading the reliability of transmission quality.
3. The routing of wires is penalized by the termination resistors positioned in a central region of the board. Generally, this region is densely populated with wires such as CA wires coming back from connectors, wires for CA output signals and DQ output signals of the LR buffers, and the like. There is no wiring space available on a surface layer because pads for mounting DRAMs, passive parts and the like are mounted on the surface layer, and the foregoing signals, generally in a bus form, cannot pass through the surface layer, and therefore pass through an inner layer. Also, since CA signals traveling through the inner layer eventually reach a termination resistor, they once appear on the surface layer through TVH (Thru Via Hole) or BVH (Blind Via Hole).
Since a group of TVH and BVH are regarded as so-called “walls” from the viewpoint of wiring, multiple TVHs and BVHs should not be generally disposed in a region densely populated with wires. However, in LR-DIMM, the termination resistor is only disposed in a region which is densely populated with wires. Since it is generally known that wires narrowly spaced from one another are susceptible to cross-talk, such crowded wires should be avoided for improved transmission quality.
4. Limitations exist in methods for routing outputs from the LR buffers (topology). Due to the positional relationship between LR buffers in LR-DIMM, even if one attempts to modify the wiring structure in order to improve the transmission quality, the only option is a wiring structure which involves discontinuous loads as shown in FIG. 5.
5. Wires are crowded around outputs of the LR buffers because a mixture of input and output CA signals and DQ signals go back and forth there. As is apparent from FIGS. 5 and 6, wires are densely crowded in the LR-DIMM due to a bus which accommodates input/output CA signals that go back and forth around the outputs of the LR buffer, and input/output DQ signals which extend radially. For the reason set forth above, such crowded wires should be avoided.